The PlayStation 4 and Xbox One may not offer an enormous jump over last-generation graphics out of the gate, but the SoCs inside the consoles — semi-custom APUs made by AMD — are a huge leap forward in terms of integration and capability. Both consoles integrate functionality that was previously broken out into multiple chips, using the most advanced 28nm process currently available. A new teardown of the PS4 gives us a look at how the SoC itself was assembled — and how Sony chose to hedge its bets a little when it came to yield.
Chipworks has published multiple die photos of the SoC, and they show us some very interesting things about how the chip was built.
First off, this should settle, beyond any question, exactly which CPU architecture the processor is based on. Despite continuing claims from some that the SoC must contain a higher-end Kaveri/Steamroller-class CPU, the tiny x86 cores implemented here are clearly based on Jaguar/Kabini. Each core is roughly 3.1 millimeters square — exactly the size AMD gave for that chip. The large (rather plaid) boxes in each quad-core arrangement are the L2 cache. Memory I/O wraps all three sides of the die, which makes sense — the SoC itself uses a GPU-style memory layout. It’s not clear from this diagram whether HSA is implemented on the chip or not, though it might be possible to identify the IOMMU unit that HSA requires with a close analysis.
Speaking of the SoC, this is one big puppy.
Die size on the chip is 328 mm sq, and the GPU actually contains 20 compute units — not the 18 that are specified. This is likely a yield-boosting measure, but it also means AMD implemented a full HD 7870 in silicon. According to Chipworks, the GPU is 88 mm sq, and takes up about a third of the total die. Looking at AMD’s published figures for the HD 7870, however, the Pitcairn GPU core is a 228 mm sq part. So which is correct? Probably both. Chipworks is only counting the cores as part of the GPU, whereas the full Pitcairn die contains memory controllers, audio processing blocks, video encode/decode hardware, the PCIe 3.0 bus interface, and a number of other low-level silicon blocks that increase total die size. The actual streaming processors are only one component.
If you ever wondered how Chipworks reverse-engineers chips to get these die shots, incidentally, read this story: How to crack open some computer chips and take your own die shots.
The Wii U’s design was a bit prophetic
One of the interesting things about the PS4′s design is how closely it echoes the Wii U’s design. While the PS4 is far, far more powerful than the Wii U, Sony made very similar decisions about where to spend its transistor budget. As some of you may recall, the Wii U’s GPU is far larger than its CPU — the latter is a triple-core version of the Broadway core that powered the Wii (which was, itself, a higher-clocked version of the GameCube CPU). The GPU, while still underpowered by current standards, integrated far more computational horsepower than the old Hollywood GPU inside the Wii.
If you look back at die sizes for the PS3 and Xbox 360 era, the CPU and GPU were very nearly equal partners. The PS4 on 28nm is still a third larger than the integrated PS3 on 40nm — if both were built at 28nm, the PS4 would be twice the size of its predecessor. This also helps explain the tension between pushing more graphics horsepower into the next generation and the need to ship a product, period. Beefing up the PS4 further would have cost more and made the chip more complex. Waiting for 20nm, when costs were more manageable, would have meant waiting a year or more while TSMC ironed out the bugs in its process. Giving the Xbox that kind of lead time was likely untenable to Sony executives.
Sony will almost certainly take the PS4 through the same die shrink process that characterized the PS3, but not for at least a year — TSMC is set to begin volume production of 20nm starting in Q1 2014, but won’t be ready to transition a part as complex as this one for quite some time.Chipworks, Wired]